1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device and its manufacturing apparatus, and more particularly to a method for forming an interlayer insulating layer for a semiconductor device having a multiple wiring layer structure and its forming apparatus.
2. Description of the Related Art
With the increase of the integrality of the semiconductor device, so-called multiple wiring layer structuring which forms wiring materials in the multiple layer form on a substrate is advancing, and a manufacturing process for such semiconductor devices having the above multiple wiring layer structure is becoming complicated and extended. In particular, the process for forming the multiple wiring layer occupies a large ratio in the production cost of the semiconductor device. To lower the cost of the semiconductor device, demands for reducing the multiple wiring layer process are increasing. And, to decrease the steps in the multiple wiring layer process, an insulating layer planarization technology is significant.
As one of the technologies for planarization of the surface of an interlayer insulating layer, an APL (Advanced Planarization Layer) process has been reported (Literature: Matsuura et al., IEEE Tech. Dig., pp 117, 1994).
In the APL process, to produce the interlayer insulating layer, SiH.sub.4 gas and an oxidizing agent H.sub.2 O.sub.2 (hydrogen peroxide solution) are reacted in a vacuum at a low temperature (e.g., approx. 0.degree. C.). And, as an intermediate product, Si(OH).sub.4 with a high flowing property is related to the reaction. As a result, a self-flowing (reflow) SiO.sub.2 film (hereinafter referred to as the reflow SiO.sub.2 film) which can be planarized on the lower wiring layer is formed.
This method can simultaneously achieve the embedding of the insulating film among wirings on the lower wiring layer and the planarization of the insulating film surface, and can complete the process up to the planarization by a single film forming, so that it can meet the demand for reducing the multiple wiring layer process.
Here, a conventional multiple wiring layer forming process will be described with reference to FIG. 1 (a) to FIG. 1 (c)
As shown in FIG. 1 (a), an element area (not shown) and others are formed on a semiconductor substrate 30, a lower insulation layer 31 is formed by an atmospheric pressure CVD method, and contact holes (not shown) are formed.
Then, a first wiring material (e.g., aluminum containing 1% of Si and 0.5% of Cu) for the lower wiring layer is deposited, and the wiring material is patterned by the photolithography method or the RIE (reactive ion etching) method to form a lower wiring layer 32.
And, a plasma CVD insulating film 33 is formed as a first interlayer insulating layer (base insulating film) on the lower wiring layer 32 by the ordinary plasma CVD method.
As shown in FIG. 1 (b), a reflow SiO.sub.2 film 34 is formed by the above-described method to embed the reflow SiO.sub.2 film 34 among the mutual wirings of the lower wiring layer 32 and to planarize the surface. The reflow SiO.sub.2 film 34 absorbs water in the process of forming the film because of its forming process and has water in it (water which was absorbed at the time of forming the film).
And, as shown in FIG. 1 (c), a second plasma CVD insulating film 35 is formed as a second interlayer insulating layer (passivating layer) on the reflow SiO.sub.2 film 34 by the ordinary plasma CVD method.
Then, the semiconductor substrate 30 is accommodated into a furnace anneal chamber and thermally treated (furnace anneal) at a high temperature of, e.g., 450.degree. C. in the atmosphere for approx. 30 minutes to discharge a water content from the reflow SiO.sub.2 film 34.
Next, etching is performed to make contact holes or via holes in the interlayer insulating layer, a second wiring material (e.g., aluminum containing 1% of Si and 0.5% of Cu) for an upper wiring layer is deposited, and the upper wiring layer (not shown) is formed by patterning.
But, the above-described conventional reflow SiO.sub.2 film 34 forming method continuously supplies SiH.sub.4 gas and H.sub.2 O.sub.2 during the deposition of the reflow SiO.sub.2 film 34, and the reflow SiO.sub.2 film 34 formed by the above method has a high dielectric constant of approx. 4.5 to 4.7 (ordinary SiO.sub.2 film by thermal oxidation has a dielectric constant of approx. 3.9).
Thus, the interlayer insulating layer containing the above reflow SiO.sub.2 film 34 has a large capacity (or, wiring capacity), and the following to the insulating film having a low dielectric constant required for high-speed MOS devices and high-speed logic circuits becomes difficult. Thus, there is a disadvantage that the application to a high-speed device becomes difficult.
When the reflow SiO.sub.2 film 34 is formed thick in order to decrease the capacity of the interlayer insulating layer containing the reflow SiO.sub.2 film 34, the discharged amount of water from the reflow SiO.sub.2 film 34 increases by the thermal treatment such as furnace anneal. And, since the reflow SiO.sub.2 film 34 is suddenly shrunk, the reflow SiO.sub.2 film 34 is cracked.
As a method to lower the above dielectric constant, it is effective to contain fluorine (F) into the reflow SiO.sub.2 film, but by the above-described conventional reflow SiO.sub.2 film 34 forming method using a low-temperature & low-pressure chemical vapor deposition (CVD) method, fluorine gas is hardly decomposed in the process of forming the reflow insulating film, so that it is difficult to include fluorine into the reflow insulating film.
Accordingly, it is necessary to devise a step of containing fluorine into the reflow insulating film. As an example, the applicant of this invention has proposed in Japanese Patent Laid Open No. 7-12410 a manufacturing method that at the time of forming the reflow SiO.sub.2 film by the low-temperature & low-pressure CVD method, a fluorine-based gas in a radical state passed through a microwave waveguide is introduced into a reaction chamber to mutually react SiH.sub.4 gas, H.sub.2 O.sub.2 and fluorine-based gas. According to this manufacturing method, when the reflow SiO.sub.2 film is formed by the low-temperature & low-pressure CVD method, fluorine can be contained into the reflow SiO.sub.2 film in the process of forming the film, and it was confirmed that the dielectric constant of the reflow SiO.sub.2 film is lowered to 3.6 or below.
As described above, the reflow SiO.sub.2 film, which is obtained when the reflow insulating film forming technology is adopted for the interlayer insulating layer forming process in the conventional multiple wiring layer process, has a disadvantage that its dielectric constant is high.